Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Clock Network
Author:
Affiliation:
1. Quality and Reliability Test Chips Design & Data Intel,Hillsboro,OR,USA
2. Quality and Reliability Test Chips Design & Data Intel,Bangalore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529398.pdf?arnumber=10529398
Reference6 articles.
1. Deterministic clock gating for microprocessor power reduction
2. Power considerations in the design of the Alpha 21264 microprocessor
3. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
4. A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation
5. An on-die all-digital delay measurement circuit with 250fs accuracy
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