A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications-Reference-Cited by-同舟云学术

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A Clock Generator With Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications

Published:2006-06 Issue:6 Volume:41 Page:1275-1285
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chen P.-L.,Chung C.-C.,Yang J.-Y.,Lee C.-Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/34322/01637592.pdf?arnumber=1637592

Cited by 31 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthesis of a Programmable Clock Management Unit Using Clock Dividers and Clock Gating using 45nm technology;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024

3. Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-05

4. A Fully Synthesizable Ultra-${N}$ Audio Frequency Multiplier for HDMI Applications;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-10

5. An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering;2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS);2019-12

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