Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
Author:
Affiliation:
1. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9763566/09703104.pdf?arnumber=9703104
Reference27 articles.
1. digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture
2. Tradeoffs between settling time and jitter in phase locked loops
3. A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators
4. Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation
5. A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs
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