Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-<tex>$mu$</tex>m CMOS-Reference-Cited by-同舟云学术

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Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-<tex>$mu$</tex>m CMOS

Published:2004-03 Issue:3 Volume:39 Page:501-510
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:en
Short-container-title:IEEE J. Solid-State Circuits

Author:

Narendra S.,De V.,Borkar S.,Antoniadis D.A.,Chandrakasan A.P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/28416/01269927.pdf?arnumber=1269927

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