Simulation-Based Recommendations for Digital Circuits Design Using Schottky-Barrier-Type GNRFET

Abstract

The use of graphene nano-ribbon field-effect transistors (GNRFETs) in the nanoscale circuits design is challenging because there are several adjustable parameters that need to be selected carefully. In this paper, we evaluate the impact of changes in different GNRFETs’ parameters including channel length (Lch), oxide thickness (Tox), line-edge roughness (Pr), number of dimer lines (N), supply voltage, and temperature on the performance of inverter, Flip-Flop, and SRAM circuits. Performance analysis in terms of noise margin (NM), delay, average power, and energy-delay-product (EDP) show that those adjustable parameters of the GNRFETs are of a significant role in attaining low-power or high-performance requirements. To achieve low-power designs, GNRFETs with perfectly smooth edges and higher Tox should be used. For low-power designs with a smaller oxide thickness, it is suggested to select 9 for N with very low Pr. Otherwise, the priority would be choosing 13 for N. To attain high-performance designs with low delay, it is recommended to use the GNRFETs without Pr. If the edges of graphene nano-ribbons are not smooth, choosing (3p+1, p ∈ ℕ ) periodic for N provides a potential improvement in circuit delay. Moreover, selecting 18 for N and smaller Tox provides a potential improvement in circuit delay.