Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation-Reference-Cited by-同舟云学术

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Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

Published:2005-01 Issue:1 Volume:40 Page:110-131
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Maxim A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/30030/01374996.pdf?arnumber=1374996

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices;IEICE Transactions on Electronics;2016

2. A delay-locked loop with self-calibration circuit for reducing phase error;Microelectronics Journal;2013-08

3. Analysis of DLL Jitter due to Voltage-Controlled Delay Line;Circuits, Systems, and Signal Processing;2013-04-11

4. Deep-Submicron CMOS Design Challenges When Integrating the RF Front-End and Digital Baseband in a Single-Chip Receiver SoC;Circuits at the Nanoscale;2008-09-09

5. A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification;IEEE Journal of Solid-State Circuits;2008-09

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