A reset-free anti-harmonic delay-locked loop using a cycle period detector-Reference-Cited by-同舟云学术

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A reset-free anti-harmonic delay-locked loop using a cycle period detector

Published:2004-11 Issue:11 Volume:39 Page:2055-2061
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Eunseok Song ,Seung-Wook Lee ,Jeong-Woo Lee ,Joonbae Park ,Soo-Ik Chae

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/29672/01347338.pdf?arnumber=1347338

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS;IEEE Solid-State Circuits Letters;2024

2. Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process;Analog Integrated Circuits and Signal Processing;2023-12-19

3. A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL;Electronics;2022-08-04

4. Overview of Analog Wide Range Delay Locked Loops;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2018-11-07

5. An all-digital DLL with duty-cycle correction using reusable TDC;International Journal of Circuit Theory and Applications;2015-08-04

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