Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process-Reference-Cited by-同舟云学术

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Published:2023-12-19 Issue:1 Volume:118 Page:121-131
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Saraji Fatemeh Esmaili,Ghorbani Alireza,Anisheh Seyed Mahmoud

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s10470-023-02203-6.pdf

Reference26 articles.

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2. Yoon, Y., Park, H., & Kim, C. (2020). A DLL-based quadrature clock generator with a 3-stage quad delay unit using the sub-range phase interpolator for low-jitter and high-phase accuracy DRAM applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(11), 2342–2346.

3. Akram, M. A., Lee, M. -H., Cho, D. -H., & Hwang, I. -C. (2020). A 0.012mm2, 0.96-mW all-digital multiplying delay-locked loop based frequency synthesizer for GPS-L4 band. In IEEE International conference on consumer electronics (ICCE) (pp. 1–2).

4. Rehman, S. U., Khafaji, M. M., Ferschischi, A., Carta, C., & Ellinger, F. (2020). A 0.2–1.3 ns range delay-control scheme for a 25 Gb/s data-receiver using a replica delay-line-based delay-locked-loop in 45-nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(5), 806–810.

5. Jeong, M., Shin, M., Kim, J., Seung, M., Lee, S., & Kim, J. (2020). Measurement and analysis of system-level ESD-induced jitter in a delay-locked loop. IEEE Transactions on Electromagnetic Compatibility, 62(5), 1840–1851.