Analysis and optimization of a SAR ADC with attenuation capacitor
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6849597/6859515/06859535.pdf?arnumber=6859535
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect;AEU - International Journal of Electronics and Communications;2022-07
2. A 0.3 V 10b 3 MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications;Analog Circuits and Signal Processing;2021-12-08
3. A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques;IEICE Electronics Express;2021-06-10
4. A Reconfigurable 0.1–10 MHz DT Passive Dynamic Zoom ADC for Cellular Receivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-07
5. A Four-Level Switching Scheme for SAR ADCs with 87.5% Area Saving and 97.85% Energy-Reduction;Circuits, Systems, and Signal Processing;2020-04-04
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