Nanoscale CMOS Biasing Circuit for Analog Applications: The Impact of NBTI Degradation
Author:
Affiliation:
1. Manipal University Jaipur,Department of Electronics and Communication Engineering,Dehmi Kalan,Jaipur,Rajasthan,India,303007
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10079844/10079947/10080544.pdf?arnumber=10080544
Reference15 articles.
1. Micro-CAP: An Analog Circuit Design System for Personal Computers
2. Modeling the Interdependences Between Voltage Fluctuation and BTI Aging
3. MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45nm and below
4. Online monitoring of NBTI and HCD in beta-multiplier circuits
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