Frequent Power-Up-and-Down-Induced Degradation of Device and Bandgap Voltage Reference in 14-nm FinFET Technology
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Published:2024-09-04
Issue:17
Volume:13
Page:3506
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Shi Yiqun1, Li Yunpeng1, Li Meng1, Xu Xin1, Zhu Hao1, Sun Qingqing1
Affiliation:
1. School of Microelectronics, Fudan University, Shanghai 200433, China
Abstract
The need for low power consumption in highly integrated systems-on-chip (SoCs), such as IoT-based smoke detection systems, has made frequent power-ups and power-downs a common practice. Although the device performance degradation caused by such frequent power-ups and power-downs is ignored in most circuit studies, in high-precision bandgap voltage references, the degradation of particular devices can result in a reference voltage shift. This work investigates the effects of frequent power-ups and power-downs on a simple bandgap reference circuit and demonstrates that the effects are real and non-negligible. Aging simulations based on simple bandgap reference circuits are performed to analyze the causes of device performance degradation and circuit output voltage shifts. The simulation results show that frequent power-ups and power-downs induce the negative bias temperature instability (NBTI) effect, a phenomenon that causes performance degradation in devices, such as threshold voltage degradation, under negative bias and high temperature conditions. Further, gate voltage waveforms of these devices were extracted for aging tests and the results of the tests in 14 nm FinFET and the NBTI aging model were used to infer the threshold voltage shift after 10 years at 125 °C. A circuit modification is proposed to mitigate the degradation of device performance and reference voltage shift. This work indicates that NBTI stresses introduced by frequent power-ups and power-downs need to be considered in circuit design.
Funder
Support Plans for the Youth Top-Notch Talents of China National Natural Science Foundation of China
Reference27 articles.
1. Hwang, W. (2003, January 17–20). New Trends in Low Power SoC Design Technologies. Proceedings of the IEEE International [Systems-on-Chip] SOC Conference, Portland, OR, USA. 2. Sun, D., Xu, S., Sun, W., Lu, S., and Shi, L. (2011, January 25–28). Low Power Design for SoC with Power Management Unit. Proceedings of the 2011 9th IEEE International Conference on ASIC, Xiamen, China. 3. Affes, H., and Auguin, M. (2015, January 26–28). SOC Power Management Strategy Based on Global Hardware Functional State Analysis. Proceedings of the 2015 Euromicro Conference on Digital System Design, Madeira, Portugal. 4. Serrano, R., Sarmiento, M., Duran, C., Nguyen, K.-D., Hoang, T.-T., Ishibashi, K., and Pham, C.-K. (2021, January 6–9). A Low-Power Low-Area SoC Based in RISC-V Processor for IoT Applications. Proceedings of the 2021 18th International SoC Design Conference (ISOCC), Jeju Island, Republic of Korea. 5. Kumaran, S., Arunachalam, S., Surendar, V., and Sudharsan, T. (2023, January 2–4). IoT Based Smoke Detection with Air Temperature and Air Humidity; High Accuracy with Machine Learning. Proceedings of the 2023 Third International Conference on Artificial Intelligence and Smart Energy (ICAIS), Coimbatore, India.
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