A Large Number of I/O Connections using Compliant Bump
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/10951/34490/01645635.pdf?arnumber=1645635
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Integration of Micro-Light-Emitting-Diode Arrays and Silicon Driver for Heterogeneous Optoelectronic Integrated Circuit Device;Japanese Journal of Applied Physics;2011-04-20
2. Characteristics of a Novel Compliant Bump for 3-D Stacking With High-Density Inter-Chip Connections;IEEE Transactions on Components, Packaging and Manufacturing Technology;2011-01
3. Compliant bump technology for back-side illuminated CMOS image sensor;2009 59th Electronic Components and Technology Conference;2009-05
4. Electroless Copper Deposition with PEG Suppression for All-Copper Flip-Chip Connections;Journal of The Electrochemical Society;2009
5. Low-Temperature 3D Chip-Stacking Using Compliant Bump;2008 10th Electronics Packaging Technology Conference;2008-12
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