A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
2. SK Hynix Inc., Icheon, South Korea
Funder
SK Hynix Inc.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/9781662/09714719.pdf?arnumber=9714719
Reference23 articles.
1. A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS
2. A 1.22ps integrated-jitter 0.25-to-4 GHz fractional-N ADPLL in 16 nm FinFET CM0S;tsai;IEEE ISSCC Dig Tech Papers,2015
3. Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops
4. Varactor characteristics, oscillator tuning curves, and am-fm conversion
5. Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture
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