Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things-Reference-Cited by-同舟云学术

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Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things

Published:2020-08 Issue:8 Volume:55 Page:2270-2284
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Cerqueira Joao P.^ORCID,Repetti Thomas J.^ORCID,Pu Yu,Priyadarshi Shivam,Kim Martha A.^ORCID,Seok Mingoo^ORCID

Funder

Qualcomm Inc. through the Qualcomm Innovation Fellowship

Catalyst Foundation

NSF

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/4/9146394/9034145-aam.pdf

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A 1–8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

3. A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip;IEEE Journal of Solid-State Circuits;2024-02

4. TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core;IEEE Journal of Solid-State Circuits;2024-02

5. An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

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