An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations
Author:
Affiliation:
1. Shanghai Jiao Tong University,Shanghai,China
2. National University of Defense Technology,Hunan,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181517.pdf?arnumber=10181517
Reference14 articles.
1. 27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications
2. Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
3. Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies
4. An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme
5. Near-threshold voltage (NTV) design
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