A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET-Reference-Cited by-同舟云学术

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

Published:2023-08 Issue:8 Volume:58 Page:2300-2313
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhu Yuanming¹^ORCID,Liu Tong¹^ORCID,Kaile Srujan Kumar¹^ORCID,Kiran Shiva¹^ORCID,Yi Il-Min¹^ORCID,Liu Ruida¹,Diaz Julian Camilo Gomez¹^ORCID,Hoyos Sebastian¹^ORCID,Palermo Samuel¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA

Funder

Semiconductor Research Corporation (SRC) Texas Analog Center of Excellence

NSF

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/4/10192489/10113477-aam.pdf

Reference29 articles.

1. A 38 GS/s 7 b time-interleaved pipelined-SAR ADC with speed-enhanced bootstrapped switch in 22 nm FinFET;zhu;Proc IEEE Custom Integr Circuits Conf (CICC),2022

2. A 10 b 1.5 GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14 nm CMOS FinFET;kull;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

3. The Bridged T-Coil [A Circuit for All Seasons]

4. A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS

5. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

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