A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing

Author:

Moon Cheol Woo1,Yoon Kwang Sub1,Lee Jonghwan2ORCID

Affiliation:

1. Department of Electronic Engineering, Inha University, Incheon 22212, Republic of Korea

2. Department of System Semiconductor Engineering, Sangmyung University, Cheonan 31066, Republic of Korea

Abstract

This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with reconfigurable SAR logic circuit and 4-bit single-slope digital ramp generator. Measurement results demonstrate the power consumption of 34.0 uW, which includes analog power of 23.8 uW and digital power of 10.2 uW, INL/DNL of ±3.5 LSB and −1.0/+2.5 LSB. The ENOB and FoM are measured to be 10.8 bits and 53 fJ/step, respectively.

Funder

National Research Foundation of Korea

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Reference15 articles.

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