Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector-Reference-Cited by-同舟云学术

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

Published:2022-10 Issue:10 Volume:57 Page:3014-3024
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ju Haram¹^ORCID,Lee Kwangho²^ORCID,Park Kwanseo³^ORCID,Jung Woosong⁴^ORCID,Jeong Deog-Kyoon⁴^ORCID

Affiliation:

1. Korea Electronics Technology Institute (KETI), Seongnam, South Korea

2. SK Hynix Inc., Icheon, South Korea

3. Department of System Semiconductor Engineering, School of Electrical and Electronics Engineering, Yonsei University, Seoul, South Korea

4. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Funder

Inter-University Semiconductor Research Center (ISRC) at Seoul National University and Technology Innovation Program

Ministry of Trade, Industry & Energy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9900477/09839462.pdf?arnumber=9839462

Reference22 articles.

1. A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

2. A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis

3. A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

4. A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET

5. A 56 Gb/s 7.7 mW/Gb/s PAM-4 wireline transceiver in 10 nm FinFET using MM-CDR-based ADC timing skew control and low-power DSP with approximate multiplier;yoo;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

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3. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

4. A 25-Gb/s PAM-4 Baud-rate CDR with High Jitter Tolerance using Shared Sampler Method;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

5. A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative DFE and Reused Comparators;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22