Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

Author:

Ju Haram1ORCID,Lee Kwangho2ORCID,Park Kwanseo3ORCID,Jung Woosong4ORCID,Jeong Deog-Kyoon4ORCID

Affiliation:

1. Korea Electronics Technology Institute (KETI), Seongnam, South Korea

2. SK Hynix Inc., Icheon, South Korea

3. Department of System Semiconductor Engineering, School of Electrical and Electronics Engineering, Yonsei University, Seoul, South Korea

4. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Funder

Inter-University Semiconductor Research Center (ISRC) at Seoul National University and Technology Innovation Program

Ministry of Trade, Industry & Energy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

3. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

4. A 25-Gb/s PAM-4 Baud-rate CDR with High Jitter Tolerance using Shared Sampler Method;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

5. A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative DFE and Reused Comparators;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

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