A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS-Reference-Cited by-同舟云学术

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

Published:2019-03 Issue:3 Volume:54 Page:672-684
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Roshan-Zamir Ashkan^ORCID,Iwai Takayuki^ORCID,Fan Yang-Hang,Kumar Ankur^ORCID,Yang Hae-Woong,Sledjeski Lee,Hamilton John,Chandramouli Soumya,Aude Arlo,Palermo Samuel^ORCID

Funder

Microelectronics Advanced Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8649832/08580386.pdf?arnumber=8580386

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