A 0.25–27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis

Author:

Komatsu YoshihideORCID,Shinmyo Akinori,Kato ShujiORCID,Funabashi MasamiORCID,Hatooka Kazuya,Fujita MayukoORCID,Tanaka Kenji,Yamasaki Aoi,Fukuda KouichiORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. A 2.1pJ/bit 56-Gb/s PAM-4 CDR with Integrated AFE in 28nm CMOS for Direct-Modulated Laser Drivers;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27

3. Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements;IEEE Design & Test;2022-10

4. Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector;IEEE Journal of Solid-State Circuits;2022-10

5. A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-09

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