Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss-Reference-Cited by-同舟云学术

Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss

Published:2023-05 Issue:5 Volume:58 Page:1462-1471
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Shen Zhengguo¹^ORCID,Shan Weiwei¹^ORCID,Du Yuxuan¹,Li Ziyu¹,Yang Jun¹^ORCID

Affiliation:

1. National ASIC Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China

Funder

National Key Research and Development Program of China

Natural Science Foundation of China

Natural Science Foundation of Jiangsu Province

Fundamental Research for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/09955629.pdf?arnumber=9955629

Reference30 articles.

1. TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

2. 31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators

3. Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

4. An energy-efficient time-domain binary neural network accelerator with error-detection in 28 nm CMOS;du;Proc IEEE Asia–Pacific Conf Circuits Syst (APCCAS),2020

5. A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock

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