TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS
Author:
Affiliation:
1. Southeast University,Nanjing,China
Funder
National Key R&D Program of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10347557/10347908/10348009.pdf?arnumber=10348009
Reference8 articles.
1. iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor
2. Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss
3. A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead
4. A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs
5. TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS
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