A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS-Reference-Cited by-同舟云学术

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS

Published:2022-05 Issue:5 Volume:57 Page:1358-1371
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhao Xiaoteng¹^ORCID,Chen Yong¹^ORCID,Wang Lin¹,Mak Pui-In¹^ORCID,Maloberti Franco²^ORCID,Martins Rui P.¹^ORCID

Affiliation:

1. State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

2. State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

Funder

Science and Technology Development Fund, Macau, SAR

Guangzhou Science and Technology Innovation and Development of Special Funds

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9761850/09686074.pdf?arnumber=9686074

Reference40 articles.

1. ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function

2. Reduction of pump current mismatch in charge-pump PLL

3. A 1.41 pJ/b 56 Gb/s PAM-4 wireline receiver employing enhanced pattern utilization CDR and genetic adaptation algorithms in 7 nm CMOS;shahramian;IEEE ISSCC Dig Tech Papers,2019

4. 6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

5. A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

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