A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS-Reference-Cited by-同舟云学术

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

Published:2023-04 Issue:4 Volume:58 Page:1062-1073
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nishi Yoshinori¹^ORCID,Poulton John W.²^ORCID,Turner Walker J.²^ORCID,Chen Xi¹,Song Sanquan¹,Zimmer Brian¹^ORCID,Tell Stephen G.²,Nedovic Nikola¹,Wilson John M.²^ORCID,Dally William J.¹^ORCID,Gray C. Thomas²^ORCID

Affiliation:

1. NVIDIA Inc., Santa Clara, CA, USA

2. NVIDIA Inc., Durham, NC, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10082904/10011563.pdf?arnumber=10011563

Reference17 articles.

1. 26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22 nm CMOS;hsueh;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2014

2. A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

3. Duty cycle measurement and correction using a random sampling technique

4. An on-die all-digital delay measurement circuit with 250fs accuracy;mansuri;Proc Symp VLSI Circuits (VLSIC),2012

5. A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface;Microelectronics Journal;2024-10

2. A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024-09

3. Ultra-low-power-consuming liquid-water-based optoelectronic computing chip;Device;2024-09

4. Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

5. A 32 Gb/s Full duplex Bi-directional Transceiver with Crosstalk Cancellation for Chiplet Interconnections;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28