Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture-Reference-Cited by-同舟云学术

Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture

Published:2022-11 Issue:11 Volume:43 Page:1850-1853
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Hsiang K.-Y.¹^ORCID,Liao C.-Y.²^ORCID,Liu J.-H.²,Lin C.-Y.²,Lee J.-Y.²,Lou Z.-F.²,Chang F.-S.²,Ray W.-C.²,Li Z.-X.²,Tseng H.-C.²,Wang C.-C.²,Liao M. H.³^ORCID,Hou T.-H.¹^ORCID,Lee M. H.²^ORCID

Affiliation:

1. Department of Electronics Engineering, Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2. Institute of Electro-Optical Engineering, National Taiwan Normal University, Taipei, Taiwan

3. Department of Mechanical Engineering, National Taiwan University, Taipei, Taiwan

Funder

Ministry of Science and Technology

Taiwan Semiconductor Research Institute (TSRI) and Nano Facility Center (NFC), Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/9927475/09877889.pdf?arnumber=9877889

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