Ultra-Deep Annular Cu Through-Silicon-Vias Fabricated Using Single-Sided Process
Author:
Affiliation:
1. School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing, China
2. BIT Chongqing Center of Microelectronics and Microsystems, Chongqing, China
Funder
National Natural Science Foundation of China
Beijing Nova Program of Science and Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/9721042/09684464.pdf?arnumber=9684464
Reference20 articles.
1. 3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating
2. Advanced Metallizatisn Processes Integration as Manufacturing Worthy Solutions for > 10:1 Aspect Ratio Mid-Process TSV
3. Enabling Continuous Cu Seed Layer for Deep Through-Silicon-Vias With High Aspect Ratio by Sequential Sputtering and Electroless Plating
4. Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias
5. Fully-Filled, Highly-Reliable Fine-Pitch Interposers with TSV Aspect Ratio >10 for Future 3D-LSI/IC Packaging
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5. Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration;Micromachines;2022-07-20
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