Unified coprocessor for high-speed AES-128 and SM4 encryption
Author:
Affiliation:
1. Shenzhen Graduate School, Peking University,Beijing,China
2. Shenzhen State Micro Technology Co., Ltd,Shenzhen,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9929429/9929329/09929737.pdf?arnumber=9929737
Reference26 articles.
1. Im provement and Implementation of SM4 Algorithm Based on FP GA;jiang;Intelligence in Networks,2021
2. A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture
3. An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
4. Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC
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3. Unified Lossless-Throughput Architecture for AES and SM4 Encryption with Changeable Keys;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
4. Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security;DEFENCE SCI J;2023
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