A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm-Reference-Cited by-同舟云学术

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A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm

Published:2010-12 Issue: Volume: Page:
ISSN:
Container-title:2010 17th IEEE International Conference on Electronics, Circuits and Systems
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Author:

Abadian Arash,Lotfizad Mojtaba,Erfani Majd Nasser,Ghaznavi Ghoushchi Mohammad Bagher,Mirzaie Hossein

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5720492/5724436/05724514.pdf?arnumber=5724514

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synchronizer-Free Digital Link Controller;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-10

2. Towards Fine-Grained DVFS in Embedded Multi-core CPUs;Lecture Notes in Computer Science;2018

3. A high-resolution time-to-digital converter using a three-level resolution;International Journal of Electronics;2015-10-05

4. A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers;Analog Integrated Circuits and Signal Processing;2015-01-11

5. Digital-only PLL with adaptive search step;International Journal of Electronics;2014-03-19

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