Column parallel single-slope ADC with time to digital converter for CMOS imager-Reference-Cited by-同舟云学术

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Column parallel single-slope ADC with time to digital converter for CMOS imager

Published:2010-12 Issue: Volume: Page:
ISSN:
Container-title:2010 17th IEEE International Conference on Electronics, Circuits and Systems
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Author:

Shin Muung,Ikebe Masayuki,Motohisa Junichi,Sano Eiichi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5720492/5724436/05724649.pdf?arnumber=5724649

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Wide-Input-Range Multi-phase Clock Generator Design for CMOS Image Sensors;2022 5th International Conference on Circuits, Systems and Simulation (ICCSS);2022-05-13

2. An 8-bit Hybrid TDC/Single-Slope ADC with an Improved Continuous-Time Comparator;Journal of Circuits, Systems and Computers;2021-07-15

3. A 1- $\mu$ s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-01

4. A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-04

5. [Paper] 3D Stacked Imager featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer;ITE Transactions on Media Technology and Applications;2016

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