A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/8325343/07904657.pdf?arnumber=7904657
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
2. A 1V 56.07dB SNDR 10MHz Bandwidth Digital Slope ADC Based on Preset Bidirectional-Shifting Technique;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. Optimal design of 10‐bit single‐slope ADC for CMOS image sensor based on swarm intelligent optimization algorithm;IET Circuits, Devices & Systems;2021-04-05
4. Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology;Circuit World;2020-02-03
5. An Asynchronous Analog to Digital Converter for Video Camera Applications;2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2019-07
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