[Paper] 3D Stacked Imager featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer-Reference-Cited by-同舟云学术

[Paper] 3D Stacked Imager featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer

Published:2016 Issue:2 Volume:4 Page:142-148
ISSN:2186-7364
Container-title:ITE Transactions on Media Technology and Applications
language:en
Short-container-title:MTA

Author:

Ikebe Masayuki¹,Uchida Daisuke¹,Take Yasuhiro²,Someya Makito¹,Chikuda Satoshi¹,Matsuyama Kento¹,Asai Tetsuya¹,Kuroda Tadahiro²,Motomura Masato¹

Affiliation:

1. Hokkaido University

2. Keio University

Publisher

Institute of Image Information and Television Engineers

Subject

Computer Graphics and Computer-Aided Design,Media Technology,Signal Processing

Link

https://www.jstage.jst.go.jp/article/mta/4/2/4_142/_pdf

Reference9 articles.

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2. 2) M. Shin, M. Ikebe, J. Motohisa and E. Sano: "Column parallel single-slope ADC with time to digital converter for CMOS imager", 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.863-866 (2010)

3. 3) T. Takahashi, H. Ui, N. Takatori, S. Sanada, T. Hamamoto, H. Nakayama, M. Akahide, T. Ueno and N. Fukushima: "A digital CDS scheme on fully column-inline TDC architecture for an APS-C format CMOS image sensor", VLSI Circuits 2011, pp.90-91 (2011)

4. 4) S. Okura, O. Nishikido, Y. Sadanaga, Y. Kosaka, N. Araki, K. Ueda, M. Tachibana and F. Morishita: "A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit", VLSI Circuits 2014, pp.1-2 (2014)

5. 5) S. Naraghi, M. Courcy and M.P. Flynn: "A 9-bit, 14μW and 0.06 mm² Pulse Position Modulation ADC in 90 nm Digital CMOS", IEEE Journal of Solid-State Circuits, 45, No.9, pp.1870-1880 (2010)