18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Author:

Ramanarayanan Rajaraman,Mathew Sanu,Sheikh Farhana,Srinivasan Suresh,Agarwal Amit,Hsu Steven,Kaul Himanshu,Anders Mark,Erraguntla Vasantha,Krishnamurthy Ram

Publisher

IEEE

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR Interface;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2023-06

2. Inhale;Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design;2022-10-30

3. HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory;2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST);2022-06-08

4. A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration;2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2022-05

5. Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC;2022 IEEE International Solid- State Circuits Conference (ISSCC);2022-02-20

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