A 2.6ps<inf>rms</inf>-period-jitter 900MHz all-digital fractional-N PLL built with standard cells-Reference-Cited by-同舟云学术

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A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells

Published:2011-09 Issue: Volume: Page:
ISSN:
Container-title:2011 Proceedings of the ESSCIRC (ESSCIRC)
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Author:

Su Richard,Lanzisera Steven,Pister Kristofer S. J.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6034695/6044880/06045005.pdf?arnumber=6045005

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS;Circuits, Systems, and Signal Processing;2021-11-10

3. A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC;AEU - International Journal of Electronics and Communications;2020-09

4. A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology;Journal of Circuits, Systems and Computers;2019-11-26

5. A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL);Integration;2017-06

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