Author:
Liu Po-Chun,Chang Hsie-Chia,Lee Chen-Yi
Cited by
5 articles.
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1. A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore;2022 19th International SoC Design Conference (ISOCC);2022-10-19
2. A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
3. Introduction;Reconfigurable Cryptographic Processor;2018
4. A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths;Lecture Notes in Computer Science;2016
5. Implementation of AES Key Schedule Using Look-Ahead Technique;Circuits, Systems, and Signal Processing;2014-06-06