A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS
Author:
Affiliation:
1. Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research),Department of Integrated Circuit Design,Singapore,138634
Funder
Institute of Microelectronics
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937760.pdf?arnumber=9937760
Reference11 articles.
1. A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm
2. 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
3. Pushing the Limits: A Very Compact and a Threshold Implementation of AES
4. A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit
5. Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design
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1. 3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Open Se Cura: First silicon results of an auditable and transparent hardware root-of-trust system using open electronic design automation in 16 nm;IEEE Solid-State Circuits Magazine;2024
3. Hardware Security in the Internet of Things: A Survey;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
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