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340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

  • Published:2015-04 Issue:4 Volume:50 Page:1048-1058
  • ISSN:0018-9200
  • Container-title:IEEE Journal of Solid-State Circuits
  • language:
  • Short-container-title:IEEE J. Solid-State Circuits

Author:

Mathew Sanu,Satpathy Sudhir,Suresh Vikram,Anders Mark,Kaul Himanshu,Agarwal Amit,Hsu Steven,Chen Gregory,Krishnamurthy Ram

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 85 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Novel High Throughput-to-Area Efficiency and Strong-Resilience Datapath of AES for Lightweight Implementation in IoT Devices;IEEE Internet of Things Journal;2024-05-15

3. Open Se Cura: First silicon results of an auditable and transparent hardware root-of-trust system using open electronic design automation in 16 nm;IEEE Solid-State Circuits Magazine;2024

4. A Compact 1,257-Gbps/W Byte-Serial AES Accelerator for IoT Applications in 22 nm;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

5. Securing an Efficient Lightweight AES Accelerator;2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom);2023-11-01
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