A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore
Author:
Affiliation:
1. The University of Electro-Communications (UEC),Tokyo,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031398.pdf?arnumber=10031398
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1. Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm
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3. Fault Detection Architectures for Post-Quantum Cryptographic Stateless Hash-Based Secure Signatures Benchmarked on ASIC;kermani;ACM Trans Embed Comput Syst,2016
4. VLSI hardware evaluation of the stream ciphers Salsa20 and ChaCha, and the compression function Rumba
5. A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
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