Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?-Reference-Cited by-同舟云学术

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Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

Published:2009-09 Issue: Volume: Page:
ISSN:
Container-title:2009 Proceedings of ESSCIRC
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Author:

Chiarella T.,Witters L.,Mercha A.,Kerner C.,Dittrich R.,Rakowski M.,Ortolland C.,Ragnarsson L.-A.,Parvais B.,De Keersgieter A.,Kubicek S.,Redolfi A.,Rooyackers R.,Vrancken C.,Brus S.,Lauwers A.,Absil P.,Biesemans S.,Hoffmann T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5307451/5325915/05325993.pdf?arnumber=5325993

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts;Semiconductors;2017-12

2. Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors;Nanoscale Research Letters;2017-02-16

3. Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter;IEEE Transactions on Electron Devices;2016-07

4. Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic;IEEE Transactions on Nanotechnology;2014-07

5. Three-dimensional Monte Carlo simulation of bulk fin field effect transistor;Chinese Physics B;2012-11

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