Novel Design Methodology Using <formula formulatype="inline"><tex Notation="TeX">$L_{\bf EXT}$</tex></formula> Sizing in Nanowire CMOS Logic-Reference-Cited by-同舟云学术

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Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic

Published:2014-07 Issue:4 Volume:13 Page:650-658
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Kaushal G.,Manhas S. K.,Maheshwaram Satish,Anand Bulusu,Dasgupta Sudeb,Singh Navab

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx7/7729/6847761/06774472.pdf?arnumber=6774472

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