Technology-Array-Algorithm Co-Optimization of RRAM for Storage and Neuromorphic Computing: Device Non-idealities and Thermal Cross-talk
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9371868/9371888/09371968.pdf?arnumber=9371968
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Electro-Thermal Cosimulation of Vertical One-Transistor–One-Resistor (1T1R) Resistive Random Access Memory and Array;IEEE Transactions on Electron Devices;2024-08
2. ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
3. Temperature-Dependent Accuracy Analysis and Resistance Temperature Correction in RRAM-Based In-Memory Computing;IEEE Transactions on Electron Devices;2024-01
4. Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27
5. Device-Architecture Co-optimization for RRAM-based In-memory Computing;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
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