Capacitor Mismatch Calibration of a 16-Bit SAR ADC Using Optimized Segmentation and Shuffling Scheme
Author:
Affiliation:
1. College of Electrical Information and Engineering, Tongji University, Shanghai, China
Funder
National Natural Science Foundation of China
Shanghai Pujiang Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10198497/10059231.pdf?arnumber=10059231
Reference12 articles.
1. All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture
2. A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier
3. A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET
4. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
5. A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs
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1. A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09
2. Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15
3. A 93.4-dB SNDR single-ended SAR ADC with a hybrid R–C DAC;Microelectronics Journal;2024-01
4. An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
5. A 16-bit 1-MS/s SAR ADC With Asynchronous LSB Averaging Achieving 95.1-dB SNDR and 98.1-dB DR;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
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