Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line-Reference-Cited by-同舟云学术

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Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line

Published:2022-01 Issue:1 Volume:69 Page:25-29
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Tong Xingyuan^ORCID,Wu Jinwu,Chen Dong

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9669084/09440538.pdf?arnumber=9440538

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

2. An Analog Delay-Locked Loop with Digital Coarse Lock Incorporating Error Compensation for Fast and Robust Locking;Electronics;2024-06-27

3. A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop;AEU - International Journal of Electronics and Communications;2024-04

4. A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

5. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS;IEEE Transactions on Microwave Theory and Techniques;2023-08

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