A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS-Reference-Cited by-同舟云学术

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A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS

Published:2023-08 Issue:8 Volume:71 Page:3596-3604
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Yang Jian¹^ORCID,Pan Quan¹^ORCID,Yin Jun²^ORCID,Mak Pui-In¹^ORCID

Affiliation:

1. School of Microelectronics and Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China

2. Department of ECE, State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics and Faculty of Science and Technology, University of Macau, Macau, China

Funder

National Natural Science Foundation of China

Natural Science Foundation of Guangdong Province

Science and Technology Plan of Shenzhen

Science and Technology Development Fund, Macau, SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/10213343/10043178.pdf?arnumber=10043178

Reference25 articles.

1. A Self-Calibrated Multiphase DLL-Based Clock Generator

2. Distributed Phase Correction Technique

3. A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop

4. A 2 – 8 GHz multi-phase distributed DLL using phase insertion in 90 nm

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1. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

2. An Analog Delay-Locked Loop with Digital Coarse Lock Incorporating Error Compensation for Fast and Robust Locking;Electronics;2024-06-27

3. An evenly-spaced-phase all-digital DLL using dual-loop SAR control;Microelectronics Journal;2024-03

4. A Shared Tdc-Based Fast-Lock All-Digital Dll Using a Dcc-Embedded Delay Line;2024

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