Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access-Reference-Cited by-同舟云学术

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Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

Published:2021-12 Issue:12 Volume:68 Page:3503-3507
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chen Jian^ORCID,Zhao Wenfeng^ORCID,Wang Yuqi^ORCID,Ha Yajun^ORCID

Funder

Natural Science Foundation of China

Science and Technology Commission of Shanghai Municipality

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9624469/09590521.pdf?arnumber=9590521

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations;IEEE Journal of Solid-State Circuits;2024

3. A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM;IEICE Electronics Express;2023-12-25

4. Low-Power 4 x 4 SRAM Memory Array Design Using Voltage Mode Technology;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02

5. A latch-based sense amplifier with improved performance for single ended SRAM application;Physica Scripta;2023-05-30

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