A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM-Reference-Cited by-同舟云学术

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A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM

Published:2023-12-25 Issue:24 Volume:20 Page:20230484-20230484
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhao Pengyuan¹,Zhao Huidong²,Yin Jialu¹,Li Zhi¹,Qiao Shushan²

Affiliation:

1. Institute of Microelectronics of Chinese Academy of Sciences

2. University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/20/24/20_20.20230484/_pdf

Reference31 articles.

1. [1] M.M.H. Galib, et al.: “Supply voltage decision methodology to minimize SRAM standby power under radiation environment,” IEEE Trans. Nucl. Sci. 62 (2015) 1349 (DOI: 10.1109/TNS.2015.2420094).

2. [2] H. Jeong, et al.: “Trip-point bit-line precharge sensing scheme for single-ended SRAM,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015) 1370 (DOI: 10.1109/TVLSI.2014.2337958).

3. [3] N. Maroof and B.-S. Kong: “10T SRAM using half-V_DD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 1193 (DOI: 10.1109/TVLSI.2016.2637918).

4. [4] Z. Lin, et al.: “A pipeline replica bitline technique for suppressing timing variation of SRAM sense amplifiers in a 28-nm CMOS process,” IEEE J. Solid-State Circuits 52 (2017) 669 (DOI: 10.1109/JSSC.2016.2634701).

5. [5] Y.-C. Chien and J.-S. Wang: “A 0.2V 32-Kb 10T SRAM with 41nW standby power for IoT applications,” IEEE Trans. Circuits Syst. I, Reg. Papers 65 (2018) 2443 (DOI: 10.1109/TCSI.2018.2792428).

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