A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/7313049/07154416.pdf?arnumber=7154416
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Low-power filter design using quasi-floating gate and level shifter approaches for biological healthcare applications;AEU - International Journal of Electronics and Communications;2024-04
2. A 10-bit 50-MS/s Asynchronous SAR ADC in 65nm CMOS;2022 IEEE 14th International Conference on Advanced Infocomm Technology (ICAIT);2022-07-08
3. A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise dynamic comparator;Analog Integrated Circuits and Signal Processing;2020-01-09
4. A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-09
5. A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique;Journal of Circuits, Systems and Computers;2019-07-31
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