A 10-bit 50-MS/s Asynchronous SAR ADC in 65nm CMOS
Author:
Affiliation:
1. School of Electronics and Information Engineering Anhui University,Hefei,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9862527/9862604/09862761.pdf?arnumber=9862761
Reference10 articles.
1. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
2. Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
3. A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS
4. A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
5. A 0.85fJ/conversion-step lOb 200kS/s subranging SAR ADC in 40nm CMOS;tai;International Solid-State Circuits Conference Digest of Technical Papers 2014 ISSCC 2014 IEEE,0
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