Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/82/27926/01246360.pdf?arnumber=1246360
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. 28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications;IEEE Transactions on Microwave Theory and Techniques;2022-04
2. A Fractional-$N$ PLL With Space–Time Averaging for Quantization Noise Reduction;IEEE Journal of Solid-State Circuits;2020-03
3. A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation;Integration;2019-03
4. A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs;IEEE Journal of Solid-State Circuits;2017-12
5. Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model;International conference KNOWLEDGE-BASED ORGANIZATION;2017-06-27
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