28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-<i>N</i> PLL for 2.4-GHz Internet-of-Things Applications-Reference-Cited by-同舟云学术

28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications

Published:2022-04 Issue:4 Volume:70 Page:2207-2216
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Gaidioz David¹^ORCID,Cathelin Andreia¹^ORCID,Deval Yann²^ORCID

Affiliation:

1. STMicroelectronics, Crolles, France

2. IMS Laboratory, University of Bordeaux, Bordeaux INP, Talence, France

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Link

http://xplorestaging.ieee.org/ielx7/22/9749140/09725247.pdf?arnumber=9725247

Reference32 articles.

1. A ?58 dBc-worst-fractional-spur and ?234 dB-FoMjitter, 5.5 GHz ring-DCO-based fractional-N DPLL using a time-invariant-probability modulator, generating a nonlinearity-robust DTC-control word;seong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

2. A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

4. Reduction of Phase Noise in Fractional-N Frequency Synthesizer Using Self-Injection Locking Loop

5. Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance;Microelectronics Journal;2024-01

2. An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS;Journal of Low Power Electronics and Applications;2023-12-17

3. A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10

4. Component-Related Phase Noise Evaluation Method for the LC Oscillators;Circuits, Systems, and Signal Processing;2023-08-09