Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet
Author:
Affiliation:
1. School of Microelectronics, Dalian University of Technology, Dalian, China
Funder
Fundamental Research Funds for the Central Universities
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9969381/09920192.pdf?arnumber=9920192
Reference15 articles.
1. A new floating point implementation of base 2 logarithm;mansour;Int J Inf Commun Eng,2014
2. An Improved Two-Step Binary Logarithmic Converter for FPGAs
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4. Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs
5. A low‐cost compensated approximate multiplier for Bfloat16 data processing on convolutional neural network inference
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